module top_fir(
	input sys_clk,
	input rst_n,
	output wire [27:0] data_out
	);
wire           clk ; 
wire	[11:0]	data; 


pllx250k pllx250k_inst(
	.inclk0(sys_clk ),
	.c0    (clk     )
	);


FIR	FIR_inst(
	 .sys_clk(sys_clk ),
    .rst_n	(rst_n	),
	 .data	(data	   )//12
);
FIR_low FIR_low_inst(
	.sys_clk (clk     ),
	.rst_n	(rst_n	),
	.data_in (data    ),
	.data_out(data_out)
);
endmodule
